High-voltage, high-cutoff-frequency electronic MOS device

ABSTRACT

An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a high-voltage,high-cutoff-frequency electronic metal-oxide semiconductor (MOS) device.Hereinafter, reference will be made, without limitation, to a DMOSdevice.

[0003] 2. Description of the Related Art

[0004] As is known, double-diffused metal-oxide semiconductor (DMOS)high-voltage devices (with a voltage higher than 20 V) have a limitedcutoff frequency. However, there are some applications where a highcutoff frequency is requested, as for example in telecommunications andespecially in wireless appliances. To try to overcome thisinconvenience, suitable technological solutions are studied to reducethe parasitic capacities associated with the devices. In fact, in DMOSdevices, the cutoff frequency F_(t) is given, in a first approximation,by: $\begin{matrix}{F_{t} = \frac{g_{m}}{2\pi \quad C_{gd}}} & (1)\end{matrix}$

[0005] where g_(m) is the transconductance of the device and C_(gd) isthe parasitic capacity existing between the gate electrode and the drainregion.

[0006] From (1) it is clear that, to maximize the cutoff frequencyF_(t), it is necessary to maximize the transconductance g_(m) and/or tominimize the parasitic capacity C_(gd).

[0007] The optimization of the parameter in the numerator is easy incase of power structures, which have a large channel perimeter; in factin this case it is possible to maximize the perimeter of the integrateddevice with the minimum length of the channel, for example makingstructures wherein the source is completely surrounded by the drainregion, so as to obtain the maximum transconductance g_(m) associatedwith the respective parasitic capacity C_(gd).

[0008] In contrast, in the case of minimum structures (that isstructures designed with the minimum dimensions compatible with theexisting voltage requirements), the layout is never optimized as regardsthe cutoff frequency. In fact, these structures present field edgestructures forming field plates and are generally formed by the gatepolysilicon so as to reduce the electric field associated with thegeometric discontinuity constituted by the field oxide (tip effect).

[0009] These edge structures surround the whole source region so as toensure that the device withstands the high voltages. An example of DMOSwith a field plate of the type described is shown in FIG. 1, where apocket 1 of N-type, forming a drain region, is surrounded by aninsulating structure 2, made in any way. A field oxide layer 3 extendson top of the pocket 1 and has a first opening 8, which surrounds anactive area 4 and a second opening 5 where a drain contact region 6 isformed, of N⁺-type. A body region 10, of P-type, is formed in the activearea 4 and houses a source region 11, of N⁺-type, and a body contactregion 12, of P⁺-type. A gate region 15 extends along the whole edge ofthe first opening 8, partly on the bird's beak-shaped portion of thefield oxide layer 3, partly on top of the active area 4. The gate region15 is electrically insulated, with respect to the pocket 1, by a thingate oxide layer, not shown, and therefore forms, with the pocket 1, aparasitic capacity C_(gd), represented by dashed lines. The sourceregion 11 and the body region 10 (through the body contact region 12)are electrically connected through a source/body contact line SB; thegate region 15 is biased through a gate contact G and the N-pocket isbiased through a drain contact D formed on the drain contact region 6.

[0010]FIG. 2 shows the profile of the masks used for forming the deviceof FIG. 1; in particular, 20 indicates the drain mask; 21 the activearea mask; 22 the gate mask; 23 the source mask and 24 the body contactmask. The gate region 15 is dashed, to show its overall form, as aclosed loop. The mask used for forming the body region 10 is notvisible, since it coincides with the three outer sides of masks 23 and24. FIG. 2 further shows the drain contact D as well as the sourcecontacts S and body contacts B connected to the source/body contact lineSB.

[0011] In the device in FIG. 1, in presence of a large parasiticcapacity C_(gd) (due to the large facing area between the gate region 15and the drain region—pocket 1—), there is a low transconductance (sincethe only channel active part is the portion of the body region 10arranged between the source region 11 and the pocket 1, below the gateregion 15; the portion of the body region 10 arranged between the bodycontact region 12 and the pocket 1 does not contribute to the formationof the device channel.

[0012] This conformation therefore does not allow a high cutofffrequency; consequently, while a power device has for example, in a 200V technology with a silicon-on-insulator (SOI) substrate, a cutofffrequency F_(t)=3.2 GHz, a minimum type device of the same voltage classhas a cutoff frequency F_(t)=2.26 GHz (exactly proportional to the ratiog_(m)/C_(gd)).

BRIEF SUMMARY OF THE INVENTION

[0013] Embodiments of the invention allow an increase of the cutofffrequency of a high-voltage device of the minimum-geometry type a highvoltage MOS device.

[0014] In particular, dividing the polysilicon region in two parts so asto disconnect the non-operative part (which forms only a field plate)from the electrically operative part, the facing area between the gateregion and the drain region is reduced, and so the parasitic capacityC_(gd) is reduced. Thereby, an increase of the cutoff frequency isobtained (which becomes equal to that of the power device), withoutincreasing the overall area of the device.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

[0015] For an understanding of the present invention, an exemplaryembodiment is now described, purely as an example without limitation,with reference to the enclosed drawings, wherein:

[0016]FIG. 1 shows a cross-section through a high-voltage,minimum-geometry MOS device of a known type;

[0017]FIG. 2 shows the layout of the masks used for the known device ofFIG. 1;

[0018]FIG. 3 shows a cross-section through a high voltage MOS deviceaccording to an exemplary embodiment of the invention; and

[0019]FIG. 4 shows the layout of the masks used for the device accordingto an exemplary embodiment of the invention in FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0020] In FIG. 3, a high voltage MOS device is indicated as a whole by30 and comprises a pocket 31 of N-type surrounded by an insulatingstructure 32. A field oxide layer 33 extends on top of the pocket 31 andhas a first opening 38 that surrounds an active area 34 and a secondopening 35 where a drain contact 36, of N⁺-type is formed. A body region40, of P-type, is formed in the active area 34 and houses a sourceregion 41, of N⁺-type, and a body contact region 42, P⁺-type. Theportion of the body region 40 between the source region 41 and thepocket 31 therefore forms a channel region 43. A polysilicon structure45, having a general shape similar to the gate region 15 of FIG. 1,extends along the whole edge of the active area 34, partly on the bird'sbeak-shaped portion of the field oxide layer 33, partly on top of theactive area 34.

[0021] The polysilicon structure 45 is divided here in two partsextending at short distances but electrically isolated and comprises agate region 46 (on the right in FIGS. 3 and 4), which surrounds on threesides the source region 41, and a non-operative region 47 (on the leftin FIGS. 3 and 4), which surrounds on three sides the body contactregion 42. In practice, the gate region 46 is only on top of the channelportion 43 of the body region 40. As may be seen in particular in FIG.4, in which the polysilicon structure 45 has been shown with dash linesfor the sake of clarity, the non-operative region 47 and the gate region46, respectively C-shaped and inverted C-shaped, are facing but extendat a reciprocal distance d comprised between the lithographic minimumobtainable with the technology used and the width L of the polysiliconstructure 45. In practice, the separation areas between the gate region46 and the non-operative region 47 have at the most a square shapefactor. This avoids introflection of the equipotential lines from thedrain region 31 towards the source region 41 which would cause highelectric field values due to the electric discontinuity. In practice,the polysilicon structure 45 maintains unchanged the field platefunctions.

[0022] Here too, the gate regions 46 and the non-operative regions 47are electrically insulated with respect to the pocket 1 by a thin gateoxide layer, not shown, and therefore form, with the pocket 1,respective parasitic capacities C_(gd) and C_(s)/C_(bd), representedwith dashed lines.

[0023] Moreover, the source region 11, the body region 10 (through thebody contact region 12) and the non-operative region 47 are electricallyconnected through a source/body contact line SB; the operative region 46is biased through a gate contact G and the pocket N is biased through adrain contact D formed on the drain contact region 36.

[0024]FIG. 4 shows the masks used for forming the device of FIG. 3; inparticular, 50 indicates the drain mask; 51 the active area mask; 52 thegate mask; 53 the source mask and 54 the body contact mask. As may beseen, the gate mask 52 has two parts 52 a, 52 b respectively for thegate region 46 and the non-operative region 47. The mask 56 of the bodyregion 40 is partially visible here since, near the opening between thenon-operative region 47 and the gate region 46, it forms twoindentations towards the inside, so as to prevent the doping agent, whenforming the body region 40, from excessively diffusing laterally andspreading towards the field oxide layer 33 in the separation areasbetween the two parts of the polysilicon structure 45. For the rest, themask 56 of the body region 40 coincides with the three outer sides ofthe masks 53 and 54. Moreover, the masks for the source 53 and the bodycontact 54 have beveled facing edges.

[0025]FIG. 4 also shows the drain contact D, as well as the source S,body B and field plate FP contacts connected to the source/body contactline SB.

[0026] Thereby, the facing area between the gate region 46 and the drainis reduced to about half, so the parasitic capacity C_(gd) is reduced bya factor of about 2. In fact, due to the electrical isolation betweenthe gate region 46 and the non-operative region 47, thesource/body-drain parasitic capacity C_(s/bd), has no influence on thecutoff frequency F_(t). Vice-versa, the transconductance g_(m) remainsunvaried, since the source perimeter undergoes no variations.Consequently there is a distinct increase (theoretically double) of thevalue of the cutoff frequency F_(t), maintaining a minimum structure.

[0027] The device 30 is made using the same manufacturing steps as thedevice of the prior art and modifying only the gate mask as shown inFIG. 4. In practice, after defining the active areas, forming the gateoxide layer (not shown) and depositing a polysilicon layer, the later isshaped (using the gate mask 52) so as to form at the same time thenon-operative region 47 and the gate region 46; then follows theimplants for the body region 40 (using the mask 56), the body contactregion 42 (using the mask 54) and the source region 41 (using the mask53). Then the contacts S, B, G, D and FP and the interconnection linesare formed.

[0028] The advantages of the described exemplary embodiment are clearfrom the above description. In particular, it is clear that the solutiondescribed allows forming devices that have tailored frequencyperformances, though having minimum bulk, and without reducing theability to withstand high voltages, which remains substantiallyunchanged, since the polysilicon structure is modified only by a minimumpart and only a minimum portion is removed (separation areas between thegate region 46 and the non-operative region 47).

[0029] Finally it is clear that numerous modifications and variationsmay be made to the device described and illustrated, all falling withinthe scope of the invention, as defined in the appended claims. Inparticular, it is stressed that the same solution is also applicable tocomplementary PDMOS structures and to structures that need a field plateformed by the gate electrode and when it is intended to reduce theparasitic capacities due to the non-operative portions of the fieldplate. Moreover, if the source and body regions are not electricallyconnected, the non-operative region 47 of the polysilicon structure maybe electrically connected to any one of the source and body regions. Thepolysilicon structure 45 may finally be divided into more than two partslocated at a short distance, if this should be necessary for designreasons.

[0030] All of the above U.S. patents, U.S. patent applicationpublications, U.S. patent applications, foreign patents, foreign patentapplications and non-patent publications referred to in thisspecification and/or listed in the Application Data Sheet, areincorporated herein by reference, in their entirety.

1. An MOS electronic device comprising: a first conductive region; afield insulating layer, covering said first conductive region; a firstopening in said field insulating layer having an edge and delimiting anactive area; a body region housed in the active area; a secondconductive region housed in the body region, a channel region formed bya portion of said body region positioned between said first and secondconductive region; and a polycrystalline silicon structure extendingalong said edge of said first opening partially on top of said fieldinsulating layer and partially on top of said active area, saidpolycrystalline silicon structure including a gate region extendingalong a first portion of said edge on top of said channel region andpartially surrounding said second conductive region, and a non-operativeregion extending along a second portion of said edge, electricallyinsulated and at a distance from said gate region.
 2. The deviceaccording to claim 1, wherein said first conductive region is a drainregion, and said second conductive region is a source region.
 3. Thedevice according to claim 2, wherein said body region houses a bodycontact region at a distance from said source region and wherein saidnon-operative region partially surrounds said body contact region. 4.The device according to claim 3, wherein said non-operative region andsaid gate region are approximately C-shaped and inverted C-shaped, witharms aligned in pairs and separated by two separation areas.
 5. Thedevice according to claim 3, wherein said non-operative region iselectrically connected to at least one of said source region and bodycontact region.
 6. The device according to claim 1, wherein said gateregion and said non-operative region have a length and are arranged at adistance between a lithographic minimum and said length.
 7. The deviceaccording to claim 4, wherein said body region has side recesses nearsaid separation areas.
 8. The device according to claim 7, wherein saidsource region and body contact region have smoothed edges facing saidside recesses.
 9. The device according to claim 2, wherein said fieldinsulating layer has a second opening and a drain contact region extendsin the drain region at said second opening.
 10. The device according toclaim 1, forming a DMOS.
 11. The process for manufacturing a MOSelectronic device comprising the steps of: forming a drain region;forming, on top of said drain region, a field insulating layer having anopening with an edge and delimiting an active area; forming a bodyregion in the active area; forming a source region in the body region,thereby a portion of said body region comprised between said sourceregion and said drain region forms a channel region; forming apolycrystalline silicon structure along said edge of said openingpartially on top of said field insulating layer and partially on top ofsaid active area to form at the same time: a gate region along a firstportion of said edge on top of said channel region and partiallysurrounding said source region, and a non-operative region along asecond portion of said edge, electrically insulated and at a distancefrom said gate region.
 12. The process according to claim 11, whereinsaid body region is so formed to house a body contact region at adistance from said source region and wherein said non-operative regionis so formed to partially surround said body contact region.
 13. Theprocess according to claim 11, wherein said non-operative region andsaid gate region are so formed to be approximately C-shaped and invertedC-shaped, with arms aligned in pairs and separated by two separationareas.
 14. The process according to claim 11, wherein said non-operativeregion is so formed to be electrically connected to at least one of saidsource region and body contact region.
 15. The process according toclaim 11, wherein said gate region and said non-operative region are soformed to have a length and are arranged at a distance between alithographic minimum and said length.
 16. The process according to claim11, wherein said body region is so formed to have side recesses nearsaid separation areas.
 17. The process according to claim 11, whereinsaid source region and body contact region are so formed to havesmoothed edges facing said side recesses.
 18. The process according toclaim 11, wherein said field insulating layer is so formed to have asecond opening and the drain region is so formed to have a drain contactregion extending in the drain region at said second opening.
 19. Theprocess according to claim 11, wherein the drain region, the fieldinsulating layer, the body region, the source region, and thepolycrystalline structure are so formed as a DMOS device.
 20. Theprocess according to claim 11, wherein the drain region, the fieldinsulating layer, the body region, the source region, and thepolycrystalline structure are so formed as a complementary PDMOSstructure.
 21. A MOS electronic device comprising: a channel regionformed by a portion of a body region positioned between first and secondconductive regions; and a polycrystalline silicon structure including: agate region extending on top of the channel region and partiallysurrounding said second conductive region, and a non-operative regionhaving a length and electrically insulated and at a distance from thegate region between a lithographic minimum and the length.
 22. The MOSelectronic device of claim 21 wherein the non-operative region and thegate region are so formed to be approximately C-shaped and invertedC-shaped with arms aligned in pairs and separated by two separationareas.
 23. The MOS electronic device of claim 21 wherein the distanceallows for a ratio of transconductance to parasitic capacitysubstantially equal to or greater than a power device of a 200Vtechnology having a cutoff frequency of 3.2 GHz.
 24. The MOS electronicdevice of claim 21 wherein the first conductive region is a drain regionand the second conductive region is a source region.